DUA1:<SYS0.SYSMAINT>EHXDH.HLP;1
===============================
1 HELP
   
     The DHV11 is an asynchronous multiplexer  that  provides  an
 interface between eight asynchronous serial data communications
 channels and any processor that supports Q 22 bus devices.
 
     EHXDH is the name of the MICRO VAX Standalone Diagnostic.   It  is
 to  be  used to verify that a DHV11 connected via Q 22 bus to a MICRO VAX
 system  is  functioning  correctly.   

1 RUN_TIME

   EHXDH takes a little over 4 minutes to run.

1 REQUIREMENTS


2 HARDWARE 
   
      o  MICRO VAX 1 family processor with a Q 22 bus configured in the
         system

      o  console terminal

      o  enough  memory  is  already  available  on  any   system
         configuration

      o  1 to 8 DHV11s
      
2 HARDCORE

      o  whole system up to but not including DHV11 should be in proper
    working order.

2 SOFTWARE 

     1.  the MICRO VAX Diagnostic Supervisor (VDS) 

          -  EHSAA.EXE - 


     2.  EHXDH.EXE - this diagnostic

     3.  EVSAA.HLP - VDS help file

     4.  EHXDH.HLP -  the  help  file  used  with  the  VDS  help
         facility

1 PREREQUISITES

   - Hardcore fully tested

1 ATTACH_DHV11

   The following is an example of how to attach the device to
   be tested, and to load and run EHXDH:


   DIAGNOSTIC SUPERVISOR.  ZZ-EHSAA-Y6.13-510   27-JAN-1984 12:00:00.00
   DS> LOAD EHXDH       ; Load the DHV11 diagnostic
   DS> ATT DHV11        ; Attach the DHV11
   DEVICE LINK? HUB     ; The option is linked to the UBA
   DEVICE NAME? TXA     ; The option named unit: 
               ; (range=A-F)
   CSR? 770000       ; The CSR address: 
               ; (range=760000-777776)
   VECTOR?  300         ; Vector address: (range=0-776)
   BR? 5          ; BR Interrupt Level: (range=4-7)

   DS> SEL TXA:         ; Select Unit Under Test    
   
   DS> START         ; Start diagnostic execution
   
      The program should now be running.
1 OPTIONS

2 LINES_TO_TEST

   The following line will be displayed:

   Lines to test [(ALL), 0,1,2,...7]

   Various responses can be given:

   ALL - Test all lines 0 - 7 in ascending order,  default on <cr>.
   n   - Any line number.
   n,m - Any combination of line numbers,  i.e  0,3,7,1.
         They will be tested in the sequence entered.

   Any invalid entry will display an error message:

   ?? Invalid response

   Followed by a reprompt of the input request.

2 BAUD_RATE

   The following line will be displayed:

   Baud Rate [(4800),50,75,110,134.5,150,300,600,1200,1800,2400 
   7200,9600,19200,38400]

   Various responses can be given:

   n - Value, or <cr> default speed of 4800.

   Any invalid entry will display an error message:

   ?? Invalid response

   Followed by a reprompt of the input request.

2 LOOP_TYPE

   The following line will be displayed:

   Loop Type [(INTERNAL), EXTERNAL, STAGGERED, ]

   Various responses can be given:

   INTERNAL - Internal loopback will be used in the test, default on <cr>.
   EXTERNAL - External loopback connect is to be used.
   STAGGERED - Staggered loopbacj connector

   Any invalid entry will display an error message:

   ?? Invalid response

   Followed by a reprompt of the input request.

   
1 EVENT_FLAGS

   o  event flag 1 - turns of Rom Version reporting

1 SUMMARY

   Not implemented

1 DEVICE

   The DHV11 option is an asynchronous multiplexer which  provides  8
   full-duplex  asynchronous  serial  data channels on Q 22 bus systems.
   The option can be used in many applications.   These  include  data
   concentration,  terminal interfacing,  and cluster controlling.

2 FEATURES

   o   Eight full duplex asynchronous data channels.
   
   o   Large 256-entry First-In-First-Out,  (FIFO),  buffer for
       received characters, dataset status changes,  and
       diagnostic information.

   o   RS-423-A/V.10/X.26 and RS-232-C/V.28 compatible.

   o   Full-duplex point-to-point or auto-answer dial-up operation.

   o   Programmable split speed per line.

   o   Total module throughput of 15000 characters per second.

   o   Automatic flow control of transmitted and received data.

   o   Self-test and background monitor diagnostics.

   o   Programmable test facilities.   

   o   All  functions  are  programmable,  except for device
       address and vector selection,  which are made by hardware
       switches on the module.

   Enough modem control is provided on all 16 channels to allow
   auto-answer dial-up operation over the Public Switched Telephone
   Network,  (PSTN).   Suitable modems to use this facility are the Bell
   models 103,  113,  212,  or equivalent.   The DHV11 can also be used
   for point-to-point operation over private lines.   Modem control  is
   imlemented by software in the host.

   By using microcomputers the DHV11 releases the host system from many
   of the data handling tasks.

   One 8051 microcomputer controls NPR transmissions from the host
   system to the DHV11.   A second 8051 controls eight SC2681 Dual
   Universal Asynchronous Receiver Transmitters,  (DUARTs),  which carry
   out the serial/parallel and parallel/serial conversion of data.

   The DHV11 carries ROM-based diagnostics which are executed
   independently of the host.   A full range of diagnostic programs is
   also available for both PDP-11 and VAX-11 systems.

   A green LED gives the GO/NO-GO status of the module.   More detailed
   diagnostic information is also made available to the host system
   via the received character FIFO.   Loopback test connectors,  built
   into each line distribution panel,  are available for use with the
   system-based diagnostics.

   I/O addresses,  interrupt vectors,  and interrupt priority for the
   module are selected on three Dual-In-Line,  (DIL),  switchpacks.   All
   other DHV11 functions and configurations are programmable.

   To prevent data loss at high throughput levels,  the DHV11 can be
   programmed for automatic X-ON and X-OFF operation.

2 PHYSICAL

   o   One 8-way distribution panel,  (H3029).

   o   Two interconnecting cables,  (BC05L-xx).

   Figure 1-1 shows major features of the module.   Its dimensions are
   21.4 cm x 39.9 cm (8.41 inches x 15.69 inches).   The module is
   connected to the backplane via connectors A-F.   J1-J4 are
   connected to the communications lines via BC05L cables and
   (H3029) distribution panels.

   DIL switchpacks E173,  E60,  and E121,  select the device address,
   the interrupt vector,  and the interrupt level,  respectively.
    
1 QUICK

   Not supported
      
1 SECTIONS

     There two sections supplied with this diagnostic;
      o  MODEM

      o  ECHO


     The modem section runs a modem loopback test and is  invoked
 by using the vds command ST/SE=MODEM.

     The ECHO section allow a  user  to  select  a  line  with  a
 terminal  attached.  All characters typed on the terminal will be
 checked for errors, then echoed back to the terminal.
 
1 Errors

   The error number appearing in the error printout corresponds
  to the error number found in each test description under errors.

  (i.e.  HELP EHXDH TEST_DESC TEST_26 ERRORS).
   
   All error numbers missing in the above help statement should
  contain enough information in the message itself to let you know whats
  going on.  

   These missing ones should only be system service errors, and
  should not occur if the HARDCORE is working correctly (see 
  HELP EHXDH ENVIRONMENT).

   The number of the line being tested when an error occurrs is
  included in the error printout.

      

1 TEST_DESC
2 Test_1 - Device Address Test
3 Test_Description -

     Verifies that the UUT will  respond  to  the  proper  Q 22 bus
 handshaking  when  accessed.   This test does not test all lines,
 just line 0.



3 Test_Steps -

     1.  verify device responds to its address



3 Errors -

      o  Error 1 - error if  device  failed  to  respond  to  its
         address

2 Test_2 - Master Reset/Selftest Test
3 Test_Description -

         execute selftest and wait for timeout  or  completion

         report  error  if  selftest  not  finished  (timeout)

         error if  selftest  did  not  complete  

    verify  no selftest  error  occurred  

   error  if  selftest  error occurred 

    verify that receive data available is  set

         error if selftest codes are unavailable or missing

         verify that the returned selftest code  is  correct

         error  if selftest code(s) are incorrect 

   read next two codes, they are  rom  version  

   verify  RX available   is  now  clear  

   error  if  data  still available after all selftest codes are read 

   verify rx  data  valid  is  now  clear 

   error if unexpected valid data in rx fifo after codes are read

3 Errors -

      o  1 - caused by master reset not clearing in 5 second

      o  2  -  caused  by  the  diagnostic  fail  bit  being  set
         indicating selftest errors

      o  3 - caused by an unexpected selftest error code

2 Test_3 - Master Reset/Skip Selftest Test
3 Test_Description -

     Verifies that the master reset bit  clears  within  a  short
 time  after  it  is  set  if  the skip selftest sequence is used.
 Verifies that the Skip Selftest return codes are normal.


3 Test_Steps -

     1.  execute skip selftest

     2.  wait for the master reset bit to clear

     3.  verify that the selftest finished

     4.  error if skip selftest failed to complete

     5.  verify that no errors occurred

     6.  error if diagnostic fail bit is set

     7.  test skip selftest codes

     8.  error if rx.avail is clear after skip selftest

     9.  error if skip selftest codes are incorrect

    10.  now read out the two ROM Version codes to clean out  the
         RX FIFO

    11.  verify there are no more valid data in the FIFO

    12.  error if rx.avail still set after all selftest codes are
         read

    13.  error if rx.valid still set after all codes are read


3 Error -

      o  Error 2 - error if skip selftest failed to complete.

      o  Error 3 - error if diagnostic fail bit is set

      o  Error 4 - error if rx.avail is clear after skip selftest

      o  Error 5 - error if skip selftest codes are incorrect

      o  Error 6 - error if rx.avail still set after all selftest
         codes are read

      o  Error 7 - error if rx.valid still set  after  all  codes
         are read


2 Test_4 - Diag Field (BMP) Test
3 Test_Description -

     Verifies that a request for BMP code reporting  is  answered
 by the UUT.


3 Test_Steps -

     1.  request the BMP code

     2.  verify bmp code was returned

     3.  error if DHU did not return BMP code

     4.  verify bmp code is correct

     5.  error if BMP code is unexpected value

     6.  verify that the RX FIFO is empty

     7.  error if rx.avail still set after BMP code is read  from
         rx fifo

     8.  error if rx.valid still set after BMP code is read  from
         rx fifo



3 Errors -

      o  

      o  Error 2 - error if DHU did not return BMP code

      o  Error 3 - error if BMP code is unexpected value

      o  Error 4 - error if rx.avail still set after BMP code  is
         read from rx fifo

      o  Error 5 - error if rx.valid still set after BMP code  is
         read from rx fifo

2 Test_5 - Selftest Forced Failure Test
3 Test_Description -

     Verifies that the selftest will report errors correctly when
 it is forced to fail, and that the diagnostic fail bit will go to
 both the active and inactive states.


3 Test_Steps -

     1.  initialized device

     2.  wait appropriate time, then write force fail code to dhu

     3.  error if selftest failed to complete

     4.  error if selftest did not detect forced error



3 Errors -

      o  Error 2 - error if selftest failed to complete

      o  Error 3 - error if selftest did not detect forced error



2 Test_6 - ROM Version Printout Test
3 Test_Description -

     If requested, reports the version numbers of the 8051 Roms.


3 Test_Steps -

      o  if event flag 1 is clear, continue, else exit

      o  init device

      o  print rom version number in returned codes


3 Errors -

      o  none



2 Test_7 - Register Address Test
3 Test_Description -

     Verifies that  the  registers  can  be  uniquely  addressed.
 Patterns  are written into the registers, and then read back.  If
 all data is not unique (barring undefined  bits)  then  an  error
 condition  exists.  Also verifies that word and and byte accesses
 work properly.  Read or write only registers, or  registers  that
 cause unwanted action are not included.  They are tested later.


3 Test_Steps -

     1.  initialize the device

     2.                 word access test

     3.  loop till lines are done

     4.  set current line number

     5.  loop until all registers have been written

     6.  write data into all indexed registers exept the ones

     7.  not implemented in RAM

     8.  loop until all lines have been verified

     9.  set up line number

    10.  loop until all indexed registers have been checked

    11.  verify patterns except for those indexed  registers  not
         implemented in RAM

    12.  error if word data read not same as word data written

    13.                                 byte access test

    14.  loop until all lines have been written

    15.  select current line

    16.  loop until all indexed registers have been written

    17.  write pattern into indexed register  expcept  those  not
         implemented in RAM

    18.  loop until all line have been verified

    19.  select current line

    20.  loop until all indexed registers have been verified

    21.  verify data in all indexed registers  except  those  not
         implemented in RAM

    22.  error if byte data read not same as byte data written

    23.                         read modify write word test

    24.  choose line zero

    25.  do the operation 10 times

    26.  increment should cause a read  modify  write  operation,
         verify data

    27.  error if read/modify/write word data read  not  same  as
         written

    28.                         read modify write byte test

    29.  choose line zero

    30.  do the operation 10 times

    31.  increment should cause a read  modify  write  operation,
         verify data

    32.  error if read/modify/write word data read  not  same  as
         written


3 Errors -

      o  Error 2 - error if word data read not same as word  data
         written

      o  Error 3 - error if byte data read not same as byte  data
         written

      o  Error 4 - error if read/modify/write word data read  not
         same as written

      o  Error 5 - error if read/modify/write word data read  not
         same as written



2 Test_8 - Id Bit Test
3 Test_Description -

     Verifies that the id bit reads as a one.


3 Test_Steps -

      o  verify ID bit is set



3 Errors -

      o  "error in device initialization, selftest codes = xxxx"

      o  "DHV11 Identification bit not set"



2 Test_9 - TX Enable/TX Action/TX Action FIFO
3 Test_Description -

     Verifies that if a data word is written without the TX  data
 valid  bit  set, no TX actions are generated, and when it is set,
 TX action is generated.


3 Test_Steps -

     1.  loop until all selected units are tested

     2.  intialize device and report selftest codes if  an  error
         occurrs

     3.  verify that TX Action has been reset

     4.  error if tx action not cleared by master reset

     5.  verify that all  TX  Enable  bits  have  inited  to  the
         correct state

     6.  error if tx enable not set by master reset

     7.  verify TX Enable clears on current line only

     8.  error if tx enable clear for line other than current one

     9.  error if current line did not have tx.ena clear

    10.  put all lines into internal loopback mode

    11.  verify TX Action remains clear when character in TX Data
         FIFO and TX Enable is clear

    12.  set line number and stuff a character  in  the  TX  Data
         FIFO

    13.  error if tx action set after data xmission when disabled

    14.  now enable transmitter, wait for character,  and  report
         error if it doesn't

    15.  show up

    16.  error if tx action not set after data transmission  when
         enabled

    17.  verify that, for some really bizarre reason,  dma  error
         did not set

    18.  error if dma error is set

    19.  verify it came in on the correct line

    20.  error if tx action occurred on wrong line

    21.  verify nothing else transmitted that character

    22.  error if more tx actions than expected

    23.  verify that each line can make  an  entry  into  the  TX
         Action FIFO

    24.  fill tx action fifo, stash any tx actions  that  may  be
         left over

    25.  wait for characters

    26.  fetch any more entries that may be there

    27.  verify that no other character came in on the same line

    28.  error if more than one txaction for current line

    29.  verify one entry for each line number

    30.  error if a line failed to return a tx action

    31.  verify that there are no more entries

    32.  error if more txactions than expected



3 Errors -

      o  Error 2 - error if tx action not cleared by master reset

      o  Error 3 - error if tx enable not set by master reset

      o  Error 4 - error if tx enable clear for line  other  than
         current one

      o  Error 5 - error if current  line  did  not  have  tx.ena
         clear

      o  Error 7 - error if tx action  set  after  data  xmission
         when disabled

      o  Error 8  -  error  if  tx  action  not  set  after  data
         transmission when enabled

      o  Error 9 - error if dma error is set

      o  Error 10 - error if tx action occurred on wrong line

      o  Error 11 - error if more tx actions than expected

      o  Error 13 - error if more than one txaction  for  current
         line

      o  Error 14 - error if a line failed to return a tx action

      o  Error 15 - error if more txactions than expected



2 Test_10 - RX Enable/Data Valid/Data Available Test
3 Test_Description -

     Verifies  that  RX  Data  Available  does  not  set  when  a
 character  is  transmitted  to  it  with RX Enable clear, RX Data
 Valid bits remains clear, and that they do set when  a  character
 is received with RX Enable set.


3 Test_Steps -

     1.  error if rx.enable bit set after reset

     2.  set line and maint mode and transmit a character

     3.  verify  that  no  character  received   while   receiver
         disabled

     4.  error if rx.avail  set  when  rx.enable  clear  and  not
         internal loop

     5.  error if rx.valid  set  with  rx.enable  clear  and  not
         internal loop

     6.  internal  loopback,  verify  that  the   character   was
         received

     7.  error if rx.avail remains clear with rx.enable clear and
         internal loop

     8.  error if rx.avail remains clear with rx.enable clear and
         internal loop

     9.  enable receiver

    10.  verify rx enable sets for current line only

    11.  error if rx.enable not set for current line

    12.  error if rx.enable set for other than current line

    13.  set dhu to current line, and transmit a character

    14.  verify that data valid and data available got set

    15.  error if rx.avail clear with rx.enable set

    16.  error if rx.valid clear with rx.enable set

    17.  verify no receiver errors occurred

    18.  error if any error bits set on received data

    19.  verify character came in on correct line

    20.  error if data came in on unexpected line

    21.  verify no other lines recevied a character

    22.  error if rx.avail is still set  after  reading  expected
         data

    23.  error if rx.valid is still set  after  reading  expected
         data



3 Errors -

      o  Error 2 - error if rx.enable bit set after reset

      o  Error 4 - error if rx.avail set when rx.enable clear and
         not internal loop

      o  Error 5 - error if rx.valid set with rx.enable clear and
         not internal loop

      o  Error 6 - error if rx.avail remains clear with rx.enable
         clear and internal loop

      o  Error 7 - error if rx.avail remains clear with rx.enable
         clear and internal loop

      o  Error 8 - error if rx.enable not set for current line

      o  Error 9 - error if rx.enable set for other than  current
         line

      o  Error 11 - error if rx.avail clear with rx.enable set

      o  Error 12 - error if rx.valid clear with rx.enable set

      o  Error 13 - error if any error bits set on received data

      o  Error 14 - error if data came in on unexpected line

      o  Error 15 - error if rx.avail is still set after  reading
         expected data

      o  Error 16 - error if rx.valid is still set after  reading
         expected data



2 Test_11 - Maintenance Mode Test
3 Test_Description -

     This test verifies that the Maintenance  modes  are  working
 correctly.  Works only in staggerred loopback mode.


3 Test_Steps -

     1.  verify all lines  inited  to  correct  maintenance  mode
         (normal mode);

     2.  error if maintenance mode did not initialize to normal

     3.  set line and put it in internal loopback mode

     4.  verify only current line is in internal loop mode

     5.  error if line failed to set to internal maintenance mode

     6.  error if internal mode set on other than current line

     7.  transmit   character   and   allow   enough   time   for
         transmission

     8.  verify that data available is set

     9.  error if rx.avail not set  after  xmission  in  internal
         loop

    10.  verify that data valid is set

    11.  error if rx.valid not set after transmission in internal
         loop

    12.  verify it came in on the correct line number

    13.  error if data received on unexpected line

    14.  verify no errors occurred

    15.  error if data received with errors

    16.  verify the data is correct

    17.  error if data received is not same as transmitted

    18.  set current line in normal mode

    19.  verify current line is normal mode

    20.  error if line failed to set to normal mode

    21.  set adjacent line in loop mode

    22.  transmit   character   and   allow   enough   time   for
         transmission

    23.  error if data not loop back  by  external  connector  in
         normal mode

    24.  error if data received on unexpected line

    25.  error if data received with errors

    26.  error if data received not same as transmitted

    27.  set line to current line again to test auto echo mode

    28.  end of testing



3 Errors -

      o  Error 2 - error if maintenance mode did  not  initialize
         to normal

      o  Error 3 - error  if  line  failed  to  set  to  internal
         maintenance mode

      o  Error 4 - error if  internal  mode  set  on  other  than
         current line

      o  Error 6 - error if rx.avail not set  after  xmission  in
         internal loop

      o  Error 7 - error if rx.valid not set  after  transmission
         in internal loop

      o  Error 8 - error if data received on unexpected line

      o  Error 9 - error if data received with errors

      o  Error 10 -  error  if  data  received  is  not  same  as
         transmitted

      o  Error 11 - error if line failed to set to normal mode

      o  Error 13 - error if  data  not  loop  back  by  external
         connector in normal mode

      o  Error 14 - error if data received on unexpected line

      o  Error 15 - error if data received with errors

      o  Error  16  -  error  if  data  received  not   same   as
         transmitted

2 Test_12 - RX FIFO Test
3 Test_Description -

     This test verifies that the fifo locations can  be  uniquely
 addressed  from  the  Q 22 bus.  The FIFO is filled with 256 unique
 bytes of data, and then checked for data integrity.


3 Test_Steps -

     1.  initialize device

     2.  set current line number, enable receiver, fill rx  silo.
         Report any tx failures

     3.  verify that the character has been xmitted

     4.  error if data failed to get transmitted

     5.  verify that csr data available bit is set

     6.  error rx.avail clears before rx fifo is empty

     7.  verify that no errors have occurred

     8.  error if data received with errors

     9.  error if data received is not same as transmitted

    10.  verify that the line number is okay

    11.  error if data received on unexpected line



3 Errors -

      o  Error 3 - error if data failed to get transmitted

      o  Error 4 - error rx.avail clears before rx fifo is empty

      o  Error 5 - error if data received with errors

      o  Error 6  -  error  if  data  received  is  not  same  as
         transmitted

      o  Error 7 - error if data received on unexpected line



2 Test_13 - Interrupts Test
3 Test_Description -

     Verifies that the TX.  and RX.  interrupts work correctly


3 Test_Steps -

     1.  initialize device

     2.  enable adapter interrupts and report any errors doing so

     3.  set interrupt enable bits and verify they are set

     4.  verify the bits aren't stuck

     5.  error if interrupt enable bits failed to set

     6.  set master reset and wait for it to get done

     7.  error if reset failed to complete

     8.  error if interrupt enable bits were  cleared  by  master
         reset

     9.  init Q 22 bus and report any errors

    10.  verify that the interrupt enable bits  were  cleared  by
         Q 22 bus init.

    11.  error if bits not cleared by Q 22 bus init

    12.  clear out the interrupt enable bits

    13.  set loopback mode for this line

    14.  transmit a character and report  any  errors  doing  so,
         then clean out the silos

    15.  clean out the silos

    16.  verify that no  interrupts  occurred  with  the  DHU/DHV
         interrupts disabled

    17.  error if interrupts occurred with interrupts disabled

    18.  enable tx interrupts only, xmit a character,  and  clean
         out silos

    19.  clean out the silos

    20.  verify  that  tx  interrupt  occurred  and  only  a   tx
         interrupt occurred

    21.  error if unexpected interrupt occurred

    22.  error if rx interrupt occurred, or tx  interrupt  failed
         to occur

    23.  verify the vector is okay

    24.  error if tx interrupt occurred at wrong vector

    25.  verify that the br level is correct.  16  is  subtracted
         since

    26.  the IPL is different by that much.

    27.  error if interrupt was requested at wrong level

    28.  clear interrupt flags, disable xmit  interrupts,  enable
         rx interrupts

    29.  xmit a character and report any errors, then  clean  out
         silo

    30.  clean out the silos

    31.  verify that a rx  interrupt  and  only  a  rx  interrupt
         occurred

    32.  error if unexpected error occurred

    33.  error if tx interrupt occurred or rx interrupt failed to
         occur

    34.  verify rx interrupted at correct vector

    35.  error if interrupt occurred at wrong vector

    36.  verify rx interrupted at correct br level

    37.  error if interrupt requested at wrong br level

3 Errors -

   o Error 5 - error if interrupt enable bits failed to set

   o Error 6 - error if reset failed to complete

   o Error 7 - error if interrupt enable bits were cleared by master reset

   o Error 9 - error if bits not cleared by Q BUS init

   o Error 12 - error if interrupts occurred with interrupts disabled

   o Error 14 - error if unexpected interrupt occurred

   o Error 15 - error if rx interrupt occurred, or tx interrupt failed to o
ccur

   o Error 17 - error if unexpected error occurred

   o Error 18 - error if tx interrupt occurred or rx interrupt failed to oc
cur




2 Test_14 - DMA Start/DMA Abort Test
3 Test_Description -

     Verifies that each DMA start bit will initiate a DMA TX on a
 line, that it can be aborted and resumed, and that DMA aborts and
 completions cause interrupts.


3 Test_Steps -

     1.  initialize device

     2.  enable interrupts Q 22 bus adapter interrupts, and dhu/dhv
         interrupts

     3.  init all diagnostic flags

     4.  set line number

     5.  set internal loop

     6.  set tx address, and count

     7.  allow time for loopback to engage

     8.  fire up the DMA and allow 1 second before timing out

     9.  see if unexpected interrupt

    10.  Error if unexpected Error occurred during DMA

    11.  check to see if the DMA completed

    12.  Error if the DMA timed out or failed to cause  interrupt
         when done

    13.  verify tx action is set

    14.  Error if DMA did not cause tx.action to set

    15.  verify no DMA errors occurred

    16.  Error if DMA Error occurred

    17.  verify that the DMA start bit has been cleared

    18.  Error if dma start bit is still set after completion

    19.  verify that no other tx action occurred

    20.  Error if unexpected tx.action in action fifo

    21.  TEST DMA ABORTS

    22.  enable adapter interrupts

    23.  enable device interrupts

    24.  create a mask to compare with txaction flags  for  lines
         that have completed

    25.  loop to set up all lines

    26.  set line number

    27.  set internal loop

    28.  setup dma

    29.  allow time for loopback to engage

    30.  set a one second timer

    31.  fire up the dma's

    32.  loop here until we are sure all dma's have been aborted

    33.  Error if all dma's not aborted within two seconds

    34.  verify everything turned out okay

    35.  verify that we have received an interrupt from  the  DMA
         abort

    36.  Error if DMA abort did not cause interrupt

    37.  verify that the DMA has truly stopped

    38.  Error if DMA abort did not stop the DMA

    39.  verify the start bit is cleared

    40.  Error if DMA abort did not clear DMA start bit

    41.  verify no dma Error occurred

    42.  Error if DMA Error is set after a DMA abort

    43.  verify no other tx action occurred

    44.  verify that the address and byte count are okay

    45.  clear abort bit and set start bit to restart the dma

    46.  set line number

    47.  clear abort, set start in buffered regs

    48.  write buffered regs to device

    49.  loop here until we are sure all dma's have been aborted

    50.  Error if all dma's not aborted within two seconds

    51.  verify that we have received an interrupt

    52.  Error if DMA did not interrupt after restart

    53.  verify the start bit is cleared

    54.  Error if DMA start bit not clear on  completion  of  DMA
         after restart

    55.  verify no dma Error occurred

    56.  Error if DMA Error bit is set after restarting the DMA

    57.  verify no other tx action occurred

    58.  Error if mor than one tx.action  in  action  fifo  after
         restart


3 Errors -

   o Error 4 - error if unexpected error occurred during DMA

   o Error 5 - error if the DMA timed out or failed to cause interrupt when
 done

   o Error 6 - error if DMA did not cause tx.action to set

   o Error 7 - error if DMA error occurred

   o Error 8 - error if dma start bit is still set after completion

   o Error 9 - error if unexpected tx.action in action fifo

   o Error 14 - error if all dma's not aborted within two seconds

   o Error 15 - error if DMA abort did not cause interrupt

   o Error 16 - error if DMA abort did not stop the DMA

   o Error 17 - error if DMA abort did not clear DMA start bit

   o Error 18 - error if DMA error is set after a DMA abort

   o Error 19 - error if unexpected tx.action in the action fifo

   o Error 21 - error if all dma's not aborted within two seconds

   o Error 22 - error if DMA did not interrupt after restart

   o Error 23 - error if DMA start bit not clear on completion of DMA after
 restart

   o Error 24 - error if DMA error bit is set after restarting the DMA

   o Error 25 - error if mor than one tx.action in action fifo after restar
t


2 Test_15 - Byte Count Register Test
3 Test_Description -

     This test  verifies  that  the  byte  count  registers  work
 properly.   Data  is  not  checked  since we are not certain that
 addressing works okay,  but  the  number  of  bytes  received  is
 tallied  for  each  line  and checked to see if it is the same as
 transmitted.


3 Test_Steps -

     1.  initialize device

     2.  enable interrupts Q 22 bus adapter interrupts, and dhu/dhv
         interrupts

     3.  set line to zero and enable interrupts

     4.  initialize received character counter,  speed,  internal
         loop, and set up dma

     5.  set internal loopback

     6.  set speed

     7.  set the address and fire up the DMA

     8.  set up a 2 minute timer in case DMA hangs

     9.  error if timeout occurred before DMA interrupted

    10.  cancel the timer

    11.  error if number of bytes received is incorrect



3 Errors -

   o Error 5 - error if timeout occurred before DMA interrupted

   o Error 7 - error if number of bytes received is incorrect



2 Test_16 - DMA Address/Byte Count Test
3 Test_Description -

     Tests the ability of the device to increment  addresses  and
 byte  counts correctly.  A DMA of 2048k bytes of decremeting data
 will be fired up and verified for data integrity and  no  errors.
 This  test  is  performed on one line only since the DMA logic is
 common to  all  lines,  and  the  memory  containing  the  lines'
 addresses  and  byte counts has been checked by the selftest.  It
 will be repeated until all address lines have been touched.


3 Test_Steps -

     1.  initialize device

     2.  enable interrupts Q 22 bus adapter interrupts, and dhu/dhv
         interrupts

     3.  set line

     4.  set DMA address and byte count

     5.  set internal loop

     6.  set line

     7.  set DMA address and byte count

     8.  set internal loopback

     9.  now fire up the DMAs

    10.  if any have completed, save the TX action or we'll  lose
         it due to

    11.  a csr read when we change the line number

    12.  set a one minute timer in case DMA hangs

    13.  error if timeout occurred before DMAs interrupted

    14.  now verify that the data has come through okay

    15.  verify that no errors occurred

    16.  verify the valid bit is set

    17.  error if no data was received

    18.  verify no errrors occurred

    19.  error if data errors occurred in received data

    20.  verify the data is correct

    21.  error if data received not same as transmitted



3 Errors -

   o Error 5 - error if timeout occurred before DMAs interrupted

   o Error 7 - error if no data was received

   o Error 8 - error if data errors occurred in received data

   o Error 9 - error if data received not same as transmitted


2 Test_17 - Speed Test
3 Test_Description -

     This test will transmit characters  at  all  speeds  on  all
 lines in internal loopback mode.  This test uses the xmit FIFO to
 send characters.


3 Test_Steps -

     1.  create a mask to compare with txaction flags  for  lines
         that have completed

     2.  initialize device

     3.  enable adapter interrupts

     4.  enable device interrupts

     5.  verify all lines inited to correct speed

     6.  error if line speed not initialized to 9600 bps

     7.  loop until all speeds are tested

     8.  set current speed

     9.  clear out the abort bit

    10.  set up dma

    11.  wait for loopbacks to take hold

    12.  fire up the dmas

    13.  set timer for one second and  transmit  until  timer  is
         done

    14.  wait for all dmas be aborted

    15.  error if all dma's not aborted within two seconds

    16.  now check number of characters xmitted

    17.  verify  that  number  of  characters  is  greater   than
         previous xmission

    18.  error if not enough characters transmitted  for  current
         speed

    19.  stash the current number of characters xmitted

    20.  speed too fast for normal check,  just  verify  TX  fifo
         filled up a couple of times

    21.  error if not enough characters transmitted  for  current
         speed

3 Errors -

   o Error 4 - error if line speed not initialized to 9600 bps

   o Error 6 - error if all dma's not aborted within two seconds

   o Error 7 - error if not enough characters transmitted for 
            current speed

   o Error 8 - error if not enough characters transmitted for 
            current speed

2 Test_18 - XON/XOFF Recognition Test
3 Test_Description -

     Verifies that XON/XOFF control is working properly


3 Test_Steps -

     1.  initialize flags

     2.  now init the device

     3.  enable adapter interrupts

     4.  set i.auto, o.auto, force xoff

     5.  verify i.auto was set

     6.  error if i.auto failed to set

     7.  verify o.auto was set

     8.  error if 0.auto failed to set

     9.  verify force xoff was set

    10.  error if force xoff failed to set

    11.  now init the device

    12.  verify  force  xoff,  i.auto,  and  o.auto  are   inited
         correctly

    13.  verify i.auto was clear

    14.  error if i.auto not cleared by initialize

    15.  verify o.auto was clear

    16.  error if o.auto not cleared by initialize

    17.  verify force xoff was clear

    18.  error if force xoff not cleared by initialize

    19.  enable device interrupts

    20.  verify force xoff sets for this line only

    21.  set line number

    22.  set internal loop if internal loop was selected

    23.  looptype is not internal, set  normal  mode  and  enable
         receiver

    24.  if staggered loop, set up adjacent line

    25.  set adjacent line number

    26.  set normal mode, and receive enable

    27.  write lcr to device and line number and restore buffered
         registers

    28.  set the force xoff bit for this line

    29.  see if current line

    30.  current line, verify bit is set

    31.  error if force xoff failed to set for this line

    32.  verify force xoff causes board  to  generate  xoffs  and
         xons

    33.  see if we have a character in the fifo

    34.  error if no data received when force xoff set

    35.  see if it is an XOFF character

    36.  error if data is not force xoff character

    37.  see if it came in on the right line

    38.  error if xoff received on unexpected line

    39.  error if xoff received on unexpected line

    40.  verify no other characters have been received

    41.  error if unexpected data in rx fifo

    42.  not the same line, verify it is clear

    43.  error if force xoff set on unexpected line

    44.  set current line again and clear force xoff

    45.  verify that it is clear

    46.  error if force xoff didn't clear for current line

    47.  wait for xon to be xmitted

    48.  get next character in RX FIFO

    49.  see if we have a character in the fifo

    50.  error if data not received when force xoff is cleared

    51.  see if it is an XON character

    52.  error if received data was not a xon character

    53.  see if it came in on the right line

    54.  staggerred loop, see if received on adjacent line

    55.  error  if  xon  not  received  on  adjacent  line   with
         staggered loop

    56.  loopback on same line

    57.  error if xon not received on current line

    58.  verify no more characters have been received

    59.  error if rx.avail still set  after  xoff/xon  characters
         read

    60.  test automatic output control function

    61.  verify that force xoff has  no  effect  when  o.auto  is
         clear

    62.  set up this line for dma

    63.  fire up the dma, wait for a few characters to xmit, then
         force xoff

    64.  now wait for xmission to complete

    65.  if timeout, then xoff probably stopped the dma and  this
         is bad

    66.  error if timeout occurred during DMA when xoff sent  and
         o.auto clear

    67.  cancel timer

    68.  clear xoff

    69.  wait for xon to be  xmitted,  and  time  for  it  to  be
         received

    70.  flush the RX and TXACTION FIFOs

    71.  clear diagnostic flags

    72.  now set automatic output control (o.auto)

    73.  set up dma again

    74.  now fire up the dma, wait a bit

    75.  force xoff, on adjacent line if staggered

    76.  not staggered, force xoff on current line

    77.  staggered, set line to adjacent line

    78.  set xoff

    79.  now allow enough time for the xmission to complete

    80.  if NO timeout, then xoff failed to suspend  transmission
         and this is bad

    81.  error if DMA completed after sending  xoff  with  o.auto
         enabled

    82.  cancel timer and clear timeout flag

    83.  clear xoff, this forces xon to be xmitted

    84.  now restore original line number

    85.  wait for dma to complete

    86.  if timeout, then xon failed to restart transmission  and
         this is bad

    87.  error if DMA timed out after sending xon after xoff with
         o.auto enabled

    88.  cancel timer, and flush the fifo

    89.  verify that o.auto can be cleared

    90.  error if o.auto failed to clear



3 Errors -

   o Error 4 - error if i.auto failed to set

   o Error 5 - error if 0.auto failed to set

   o Error 6 - error if force xoff failed to set

   o Error 8 - error if i.auto not cleared by initialize

   o Error 9 - error if o.auto not cleared by initialize

   o Error 10 - error if force xoff not cleared by initialize

   o Error 13 - error if force xoff failed to set for this line -

   o Error 16 - error if no data received when force xoff set

   o Error 17 - error if data is not force xoff character

   o Error 18 - error if xoff received on unexpected line

   o Error 19 - error if xoff received on unexpected line

   o Error 20 - error if unexpected data in rx fifo

   o Error 21 - error if force xoff set on unexpected line

   o Error 22 - error if force xoff didn't clear for current line

   o Error 25 - error if data not received when force xoff 
            is cleared

   o Error 26 - error if received data was not a xon character

   o Error 27 - error if xon not received on adjacent line 
            with staggered loop

   o Error 28 - error if xon not received on current line

   o Error 29 - error if rx.avail still set after xoff/xon 
            characters read

   o Error 31 - error if timeout occurred during DMA when xoff 
            sent and o.auto clear

   o Error 35 - error if DMA completed after sending xoff with 
            o.auto enabled

   o Error 37 - error if DMA timed out after sending xon after 
            xoff with o.auto enabled

   o Error 38 - error if o.auto failed to clear




2 Test_19 - Data Format Test
3 Test_Description -

         This test will check out that all sizes and formats work
 properly.  10 characters will be used in this test, and each line
 will be checked out.


3 Test_Steps -

     1.  initialize flags and device

     2.  enable device interrupts

     3.  set line number, loopback type and speed

     4.  set current line parameters

     5.  set up for 10 byte dma

     6.  fire up the DMAs

     7.  see if TXACTION was set, stach it if it was

     8.  set dma start bit

     9.  set a timer

    10.  wait for all the DMAs to complete

    11.  wait one more second for all the data to go through

    12.  verify that no timeout occurred

    13.  error if DMAs timed out

    14.  cancel the timer

    15.  verify no errors occurred

    16.  verify that the dma error bit is clear

    17.  error if a DMA error occurred

    18.  verify that no data or receive errors occurred

    19.  verify no receiver errors occurred

    20.  error if data received with errors

    21.  verify data is okay

    22.  error if data received is not same as transmitted



3 Errors -

   o Error 5 - Error if DMAs timed out

   o Error 6 - Error if a DMA error occurred

   o Error 7 - Error if data received with   errors

   o Error 8 - Error if data received is not same as transmitted

2 Test_20 - Modem Signal Test
3 Test_Description -

     Verifies that changing the UUT line control DTR bit  affects
 the  state  of  the dtr control line, looped signals, and that no
 unexpected bits are set, and verifies that changing the UUT  line
 control rts bit affects the state of the rts control line.


3 Test_Steps -

     1.  initialize the diagnostic flags and the device

     2.  enable interrupts

     3.  set device interrupt enable bits

     4.  set dtr, rts, and link bits

     5.  verify all the bits set

     6.  error if DTR, RTS or LINK bits of the lcr failed to set

     7.  now reset the device

     8.  error if reset to clear modem control bits timed out

     9.  clear out all selftest codes

    10.  set line number and fetch LCR and LSR

    11.  verify that all modem control and status were cleared by
         master reset

    12.  error if reset failed to clear modem control and  status
         bits

    13.  set line number

    14.  see if link should be set on current line,  or  adjacent
         line

    15.  now set link bit

    16.  now restore line

    17.  set DTR link bit

    18.  allow time for device to read modem signals

    19.  check that dtr and rts is clear on all other  lines  but
         current one

    20.  set line number and fetch LCR

    21.  see if this is the current line

    22.  yes it is, verify that DTR is set

    23.  error if DTR failed to set for current line

    24.  verify that RTS is not stuck to DTR

    25.  error if rts is set for current line

    26.  not current line, verify that DTR is clear

    27.  error if DTR set for line other than current line

    28.  see if we are in staggerred loopback

    29.  staggerred loop, see if this line has bits set

    30.  not the adjacent line, verify RING and DSR are clear

    31.  error if DSR and RING are set on unexpected line

    32.  verify link bit is not set on unexpected line

    33.  yes, adjacent line, verify that DSR and RING are set

    34.  error if DSR and RING not set on expected line

    35.  verify that CTS and DCD are not stuck to them

    36.  error if CTS and DCD are unexpectedly set

    37.  verify link bit is not unexpectedly clear

    38.  error if link bit not set on adjacent line

    39.  check for correct interrupt on modem status change

    40.  error if status change did not occur, or did  not  occur
         correctly

    41.  H325 single line loopback, see if this  is  the  current
         line

    42.  current line, verify that RING and DSR are set ;  H325

    43.  error if ring and dsr are not set  for  current  line  ;
         H325

    44.  verify that CTS and DCD are not stuck to them ;  H325

    45.  error if cts and dcd are unexpectedly set with  dtr  set
         and rts clear ;  H325

    46.  not current line, verify DSR and RING are clear ;  H325

    47.  error if dsr and ring set on unexpected line ;  H325

    48.  restore line and clear DTR

    49.  verify that it is clear

    50.  error if dsr failed to clear

    51.  wait for status to change

    52.  see if this is staggered mode

    53.  fetch LSR and verify that RI and DSR are clear

    54.  error if ring and dsr failed to clear

    55.  verify interrupt for modem status change

    56.  set RTS

    57.  verify that RTS got set on this line only

    58.  set line number and fetch LCR

    59.  if current line, make sure RTS is set

    60.  error if rts failed to set for current line

    61.  not current line, so make sure it is clear

    62.  error if rts set on unexpected line

    63.  verify RING and DCD are the only bits  set  and  on  the
         correct line

    64.  check for staggered loop

    65.  staggered loop, see if this is the adjacent line

    66.  error if cts or dcd clear on current line  in  staggered
         loop

    67.  verify the other bits are not set

    68.  error if dsr or ring are set with dtr clear and rts  set
         in staggered loop

    69.  check for correct interrupt on modem status change

    70.  error if status change did not occur, or did  not  occur
         correctly

    71.  not correct line, see if the bits are clear

    72.  error if cts and dcd set on unexpected line in staggered
         loop

    73.  single line loopback, see if this is the correct line

    74.  current line, verify CTS and DCD are set

    75.  error if cts and dcd clear on  current  line  with  h325
         loop

    76.  verify no other bits are set

    77.  error if dsr or ring set with dtr clear and rts  set  in
         h325 loop

    78.  check for correct interrupt on modem status change

    79.  error if status change did not occur, or did  not  occur
         correctly

    80.  error if cts or dcd set on unexpected line in h325 loop

    81.  now restore line

    82.  clear RTS

    83.  verify that it is clear

    84.  error if rts failed to clear

    85.  see if this is staggered loop

    86.  set adjacent line number for staggered loop

    87.  fetch LSR and verify that CTS and DCD are clear

    88.  error if cts and dcd failed to clear when rts cleared

    89.  verify interrupt for modem status change

    90.  error no clearing  RTS  failed  to  cause  modem  status
         change

    91.  clear link bit



3 Errors -

   o Error 4 - error if DTR, RTS or LINK bits of the lcr failed to set

   o Error 5 - error if reset to clear modem control bits timed out

   o Error 6 - error if reset failed to clear modem control and 
            status bits

   o Error 7 - error if DTR failed to set for current line

   o Error 8 - error if rts is set for current line

   o Error 9 - error if DTR set for line other than current line

   o Error 10 - error if DSR and RING are set on unexpected line

   o Error 12 - error if DSR and RING not set on expected line

   o Error 13 - error if CTS and DCD are unexpectedly set

   o Error 14 - error if link bit not set on adjacent line

   o Error 15 - error if status change did not occur, or did not 
            occur correctly

   o Error 16 - error if ring and dsr are not set for current 
            line ; H325

   o Error 17 - error if cts and dcd are unexpectedly set with 
            dtr set and rts clear ; H325

   o Error 19 - error if dsr and ring set on unexpected line 
            ; H325

   o Error 20 - error if dsr failed to clear

   o Error 21 - error if ring and dsr failed to clear

   o Error 23 - error if rts failed to set for current line

   o Error 24 - error if rts set on unexpected line

   o Error 25 - error if cts or dcd clear on current line   
            in staggered loop

   o Error 26 - error if dsr or ring are set with dtr clear 
            and rts set in staggered loop

   o Error 27 - error if status change did not occur, or did 
            not occur correctly

   o Error 28 - error if cts and dcd set on unexpected line 
            in staggered loop

   o Error 29 - error if cts and dcd clear on current line with 
            h325 loop

   o Error 30 - error if dsr or ring set with dtr clear and rts 
            set in h325 loop

   o Error 31 - error if status change did not occur, or did not 
            occur correctly

   o Error 32 - error if cts or dcd set on unexpected line in 
            h325 loop

   o Error 33 - error if rts failed to clear

   o Error 34 - error if cts and dcd failed to clear when rts cleared

   o Error 35 - error no clearing RTS failed to cause modem 
            status change


2 Test_21 - Framing Error/Break Bit Test
3 Test_Description -

     Verifies that forced framing errors are reported correctly.


3 Test_Steps -

     1.  set up the line

     2.  set up the adjacent line to different data size

     3.  set current line and transmit the character

     4.  verify that the adjacent line got a framing error

     5.  error if no frame  error  when  transmit  data  size  is
         different from receive

     6.  print framing error test skipped

     7.  set break bit and loop mode

     8.  now wait a second, then verify that framing error is set
         for all lines

     9.  set break bit

    10.  see if this is staggered loop mode

    11.  yes, set line to adjacent line

    12.  error if setting break bit did not cause framing error



3 Errors -

    o Error 2 - error if no frame error when transmit data size 
         is different from receive

    o Error 3 - error if setting break bit did not cause 
         framing error


2 Test_22 - Parity Generation/Detection Test
3 Test_Description -

   Verifies that all selected lines can detect
 Parity errors.  Runs only if staggered loopback is
 selected.



3 Test_Steps -

     1.  see if staggered loop

     2.  initialize the device

     3.  set line

     4.  enable receiver and parity to odd

     5.  set adjacent line to opposite parity

     6.  enable receiver

     7.  enable parity and set it to opposite parity

     8.  transmit a character and wait for it

     9.  see if current line got a parity error

    10.  error  if  no  parity  error  when  transmit  parity  is
         different from receive parity



3 Errors -

      o  Error 2 - error if no parity error when transmit  parity
         is different from receive parity



2 Test_23 - Overrun Detection Test
3 Test_Description -

         Verifies that the UUT will receive the maximum number of
 characters  without  causing and overrun error, and that one more
 character will cause overrun.


3 Test_Steps -

     1.  set internal loopback mode

     2.  overfill rxfifo

     3.  wait for xmit then clear out the tx action

     4.  read 255 characters

     5.  verify no overrun error occurred

     6.  error if overrun error occurred unexpectedly

     7.  verify the next character has overrun error and is null

     8.  error if overrun error bit is not set

     9.  verify the character is a null character

    10.  error if data with overrun is not null character



3 Errors -

      o  Error 2 - error if overrun error occurred unexpectedly

      o  Error 3 - error if overrun error bit is not set

      o  Error 4 -  error  if  data  with  overrun  is  not  null
         character



2 Test_24 - Exerciser Test

3 Test_Description -
         This test will get all lines transmitting  at  the  same
 time.   The  speed used will be 4800 bps as that is what the spec
 says the        DHU can run at with all lines full  duplex.   All
 lines will be set       up,  then  the  DMAs will be fired off as
 quickly as possible.  1024      byte buffers  will  be  used  for
 transmission and reception.  The        format  will be 8 bit, no
 parity, and 1 stop bit.


3 Test_Steps -

     1.  initialize device

     2.  enable adapter interrupts

     3.  enable device interrupts

     4.  set up necessary stuff

     5.  set address

     6.  set line speed, enaable parity, set maintenance mode

     7.  set internal loopback if selected

     8.  if staggered loopback, enable adjacent line

     9.  enable receiver

    10.  restore line number

    11.  now write all that into the device registers

    12.  delay for loopbacks to take affect

    13.  enable a timer

    14.  fire up all the DMAs

    15.  save tx action if one has completed

    16.  set line number and start it up

    17.  wait for all the DMAs to complete

    18.  wait one more second for all the data to go through

    19.  verify that no timeout occurred

    20.  error if timceout occurred before DMAs completed

    21.  cancel the timer

    22.  verify that no errors occurred

    23.  verify that the dma error bit is clear

    24.  error if DMA errors occurred

    25.  verify that all data was received

    26.  error if not all data received

    27.  verify that no data or receive errors occurred

    28.  verify no receiver errors occurred

    29.  error if data received with errors

    30.  verify data is okay

    31.  error if data received is not same as data transmitted




3 Errors -

    o Error 4 - error if timceout occurred before DMAs completed

    o Error 6 - error if DMA errors occurred

    o Error 7 - error if not all data received

    o Error 8 - error if data received with errors

    o Error 9 - error if data received is not same as data transmitted




2 Test_25 - Modem Loop Test

3 Test_Description -

        This test runs on a modem that is in loopback mode, or  a
 remote modem in remote loopback mode.
 3 Test Steps -

     1.  enable adapter and device interrupts

     2.  set line number and speed

     3.  enable the receiver

     4.  set up and fire up dma

     5.  set a two minute timer

     6.  wait for the device to complete

     7.  verify that a timeout did not occurr

     8.  error if timeout occurred before DMA completed

     9.  verify data

    10.  verify no receive errors occurred

    11.  error if data was received with errors

    12.  verify no data errors occurred

    13.  error if data received was not same as transmitted




3 Errors -

    o Error 4 - error if timceout occurred before DMAs completed

    o Error 6 - error if DMA errors occurred

    o Error 7 - error if not all data received

    o Error 8 - error if data received with errors

    o Error 9 - error if data received is not same as data transmitted




2 Test_26 - Terminal Echo Test
3 Test_Description -

        This test loops back all characters received on  a  line.
 The     operator  is  queried  as to which line the data is to be
 echoed to.      This will allow isolation of the direction a line
 may be failing.  Type control C to exit test.



3 Test_Steps -

     1.  initialize device

     2.  enable adapter and device interrupts

     3.  set line number and speed

     4.  enable the receiver for this line

     5.  see if a character has been typed

     6.  transmit all characters that we have received

     7.  verify received character has no errors

     8.  error if data received with errors

     9.  set a timer

    10.  transmit and wait for the character

    11.  verify no timeout occurred

    12.  error if timeout before character was transmitted

    13.  cancel timer and reset interrupt flag




3 Errors -

      o  Error if data received with errors


2 Test_27 - I.AUTO Test

3 Test_Description -

     Verifies the i.auto bit works correctly



3 Assumptions -

     All previous tests have successfully run



3 Test_Steps -

     1.  initialize flags

     2.  now init the device

     3.  enable adapter interrupts

     4.  enable device interrupts

     5.  START OF AUTOMATIC INPUT CONTROL TESTING

     6.  set device to current line

     7.  enable receivers

     8.  staggered loop, set line to adjacent one

     9.  enable receiver

    10.  fill the RX fifo with data

    11.  wait for character to go

    12.  error if xmit timed out

    13.  verify no xoff or xons transmitted when i.auto clear

    14.  error if xoff in rx fifo when filled past 3/4 and i.auto
         clear

    15.  verify i.auto sets for this line only

    16.  see if this is the current line under test

    17.  same line, verify it is set

    18.  error if i.auto failed to set on current line

    19.  not the current line under test, verify its clear

    20.  error if i.auto set on other than current line

    21.  reset line number

    22.  if staggered mode, set line to adjacent line

    23.  fill rx fifo past 3/4 full to make it xmit xoff

    24.  wait for character to go

    25.  error if xmit timed out

    26.  read data until an xoff is encountered

    27.  error if xoff not xmitted with i.auto enabled

    28.  error if xoff occured way beyond it's appointed time

    29.  error if xon not xmitted with i.auto enabled

    30.  error if xon occured way beyond it's appointed time

    31.  now shut off automatic output control

    32.  reset original line number

    33.  make sure i.auto for current line is clear

    34.  flush fifo

3 ERRORS: -

   o Error 4 - error if xmit timed out

   o Error 5 - error if xoff in rx fifo when filled past 
            3/4 and i.auto clear

   o Error 6 - error if i.auto failed to set on current line

   o Error 7 - error if i.auto set on other than current line

   o Error 8 - error if xmit timed out

   o Error 9 - error if xoff not xmitted with i.auto enabled

   o Error 10 - error if xoff occured way beyond it's appointed time

   o Error 11 - error if xon not xmitted with i.auto enabled

   o Error 12 - error if xon occured way beyond it's appointed time





2 Test_28 - Split Speed Test Part A

3 Test_Description - -

     This  test  verifies  that  split  speed   operations   work
  correctly This test works in staggered loopback only.



3 Assumptions -

      o  all hardware up to (but not  including)  the  device  is
         working

      o  previous tests have successfully run, otherwise  results
         may be meaningless




3 Test_Steps -

     1.  create a mask to compare with txaction flags  for  lines
         that have completed

     2.  enable adapter interrupts

     3.  enable device interrupts

     4.  loop for line speeds

     5.  loop for adjacent line speeds

     6.  clear line setup mask

     7.  loop to set up all lines

     8.  set line number and speed

     9.  enable receiver

    10.  set dma address and byte count

    11.  flag this line as set up

    12.  set up adjacent line

    13.  set speed

    14.  enable receiver

    15.  set dma address and byte count

    16.  flag this line as having been set up

    17.  set a one second timer

    18.  fire up the dma's

    19.  fire up the adjacent line

    20.  flag it as started

    21.  loop here until we are sure all dma's have been aborted

    22.  see if this line has been checked yet

    23.  flag line as having been checked

    24.  verify this lines speeds are okay

    25.  error if transmit speed did not set to correct speed

    26.  error if receive speed did not set to correct speed

    27.  verify data for line

    28.  error if data received with errors or invalid

    29.  error if data received on  adjacent  line  not  same  as
         transmitted

    30.  flag adjacent line as already tested

    31.  verify this lines speeds are okay

    32.  error if transmit or receive speeds are not  at  correct
         speed

    33.  verify the TX count is okay

    34.  error if less data than expected was transmitted

    35.  now verify adjacent line

    36.  set line to adjacent line

    37.  error if data received with errors on the other line

    38.  error if data received not same as transmitted

    39.  verify the TX count is okay

    40.  error if less data than expected was transmitted

    41.  reset setup flags and adjacent speed table

3 Errors -

   o Error 5 - error if transmit speed did not set to correct speed

   o Error 6 - error if receive speed did not set to correct speed

   o Error 7 - error if data received with errors or invalid

   o Error 8 - error if data received on adjacent line not same 
            as transmitted

   o Error 9 - error if transmit or receive speeds are not at 
            correct speed

   o Error 10 - error if less data than expected was transmitted

   o Error 11 - error if data received with errors on the other line

   o Error 12 - error if data received not same as transmitted

   o Error 13 - error if less data than expected was transmitted





2 Test_29 - Split Speed Test Part B

3 Test_Description -

     This  test  verifies  that  split  speed   operations   work
  correctly This test works in staggered loopback only.



3 Assumptions -

      o  all hardware up to (but not  including)  the  device  is
         working

      o  previous tests have successfully run, otherwise  results
         may be meaningless

3 Test_Steps -

     1.  create a mask to compare with txaction flags  for  lines
         that have completed

     2.  enable adapter interrupts

     3.  enable device interrupts

     4.  loop for line speeds

     5.  loop for adjacent line speeds

     6.  clear line setup mask

     7.  loop to set up all lines

     8.  set line number and speed

     9.  enable receiver

    10.  set dma address and byte count

    11.  flag this line as set up

    12.  set up adjacent line

    13.  set speed

    14.  enable receiver

    15.  set dma address and byte count

    16.  flag this line as having been set up

    17.  set a one second timer

    18.  fire up the dma's

    19.  fire up the adjacent line

    20.  flag it as started

    21.  loop here until we are sure all dma's have been aborted

    22.  see if this line has been checked yet

    23.  flag line as having been checked

    24.  verify this lines speeds are okay

    25.  error if transmit speed did not set to correct speed

    26.  error if receive speed did not set to correct speed

    27.  verify data for line

    28.  error if data received with errors or invalid

    29.  error if data received on  adjacent  line  not  same  as
         transmitted

    30.  flag adjacent line as already tested

    31.  verify this lines speeds are okay

    32.  error if transmit or receive speeds are not  at  correct
         speed

    33.  verify the TX count is okay

    34.  error if less data than expected was transmitted

    35.  now verify adjacent line

    36.  set line to adjacent line

    37.  error if data received with errors on the other line

    38.  error if data received not same as transmitted

    39.  verify the TX count is okay

    40.  error if less data than expected was transmitted

    41.  reset setup flags and adjacent speed table

3 Errors -

   o Error 5 - error if transmit speed did not set to correct speed

   o Error 6 - error if receive speed did not set to correct speed

   o Error 7 - error if data received with errors or invalid

   o Error 8 - error if data received on adjacent line not same 
            as transmitted

   o Error 9 - error if transmit or receive speeds are not at 
            correct speed

   o Error 10 - error if less data than expected was transmitted

   o Error 11 - error if data received with errors on the other line

   o Error 12 - error if data received not same as transmitted

   o Error 13 - error if less data than expected was transmitted

